Abstract: The rapid development of artificial intelligence (AI) and Internet of things (IoT) technologies has increased demands for the computing energy efficiency, and terminal devices are also facing great challenges in terms of hardware resource overhead. In order to solve the problem of energy efficiency, new designs of approximate computing units with low power have been widely studied. In application scenarios such as digital signal processing and image processing, there are a large number of floating-point operations. These applications consume a lot of hardware resources. However, they have certain fault tolerance characteristics and do not have to perform accurate calculations. In this paper, we propose a 32-bit single-precision reconfigurable approximate floating-point multiplier design method based on multiplication to shift addition (MTA) and asymmetric truncation. Firstly, we utiliz an efficient and low-power approximate algorithm that transforms multiplication into shift-addition for partial operands. Secondly, to ensure a balance between accuracy and cost, we propose asymmetric truncation processing for the most significant bits (MSBs) and perform precise calculations on the truncated retained parts. The design achieves high precision and low power. A wide design space is generated by combining the MTA algorithm with different bit widths and varying the number of rows in the partial product array after truncation. This allows for various trade-offs between accuracy and cost. Compared with the exact floating-point multiplier, MTA5T5 has an accuracy loss of mean relative error distance (MRED) of only about 0.32%, a power reduction of 85.80%, and an area reduction of about 79.53%. The accuracy loss of MTA3T3 with lower accuracy is about 1.92%, while the power and area decrease to 90.55% and 85.80%, respectively. Ultimately, we test the application of FIR filtering and image processing, and the results show that the proposed design has significant advantages in terms of accuracy.