Abstract: With the development of the RISC-V open-source ecosystem, driving Domain-Specific Architectures (DSAs) with custom extension instructions based on RISC-V has become a widely recognized design approach. However, under traditional hardware description languages and design paradigms, integrating DSAs with processors and completing instruction design requires significant manpower and time costs to understand processor design details and modify them. Currently, some work supports developers in accessing DSAs by implementing fixed data paths and interfaces in sequential processors. Yet, for high-performance out-of-order processors, there is no comprehensive solution available. This paper, through practice, summarizes the key issues that need to be addressed when driving and integrating DSAs with out-of-order processors using extension instructions. It designs a hardware programming framework for instruction extension targeted at high-performance out-of-order RISC-V processors, assisting developers in integrating DSAs and completing instruction extensions on out-of-order processors. The framework is implemented in Chisel, applying object-oriented and functional programming features to flexibly describe hardware and assist in completing signal connections, thereby saving developers’ effort. Our evaluation shows that with the help of this framework, developers can save up to 1000 lines of Chisel code effort, equivalent to over 10000 lines of Verilog code effort. Moreover, compared to the traditional manual modification of pipelines, the framework can save developers over 9000 lines of code reading work. The evaluation results indicate that the framework significantly reduces the manpower and time costs for developers and lowers the development threshold.