Abstract: Hybrid bit-width block floating point (BFP) offers a flexible solution for low bit-width convolution computations, optimizing storage efficiency and computational precision. Recent researches have deployed hardware solutions such as field programmable gate arrays (FPGAs) for hybrid bit-width BFP-based convolution accelerations, but they tend to underutilize FPGA resources by overlooking the full potential of digital signal processors (DSPs). This work develops a novel FPGA-based BFP convolution processing unit, termed “BE-HB”, capable of coupling two sets of BFP convolution calculations in dual-mode bit-width (i.e., 8- or 16-bit) using a single DSP for high performance. We then provide a mapping approach to streamline the computation of two sets of BFP convolutions across 8- or 16-bit data width within the DSP. Compared with representative baseline methods, our proposed design achieves better performance and lower resource consumption while maintaining model accuracy.