Abstract: Benefiting from advances in superconducting materials and the great potential of rapid single-flux-quantum (RSFQ) logic for high-performance computing, RSFQ circuits are expected to have broad application prospects in future computing technologies. However, due to their ultra-high operating frequencies, RSFQ circuits encounter severe timing challenges during physical design, necessitating the introduction of length-matching constraints at the routing stage. Simultaneously, with advancements in process nodes, routing layers now support routing across logic gate columns. To address these issues, this paper proposes a multi-channel aware routing algorithm with length-matching for RSFQ circuits. The algorithm constructs width-minimized initial routing paths by employing a cross-graph-based passive transmission line (PTL) allocation method and a routing area minimization strategy, combined with via generation and monotonic river routing. Furthermore, it introduces a diffusion-routing-based area adjustment method to reconfigure routing resources and effectively reduce resource waste. Finally, a direction-based wire length extension method is utilized to enhance global resource utilization, thereby optimizing the total circuit area. Experimental results demonstrate that, for a 16-bit RSFQ-Sklansky adder, the proposed algorithm reduces the routing area by 55%, 44%, and 12% compared to existing algorithms. Additionally, in randomly generated connection test cases, the routing area is reduced by 74%, 73%, 36%, 15%, and 7%, respectively, indicating the achievement of high-quality routing results.