Abstract: Transistor sizing optimization for analog amplifiers is challenging in automated analog-circuit design because of its large, high-dimensional design space, strong parameter sensitivity, and stringent industrial process constraints. Existing large language model (LLM)-based methods often operate inefficiently in iterative simulation-in-the-loop optimization and may repeatedly explore similar or ineffective regions. To overcome these limitations, this work proposes two complementary techniques. First, an experience-reuse-enhanced search mechanism structures and stores domain knowledge and parameter-adjustment experience generated during successful reasoning in an experience repository. This repository supports cross-task knowledge reuse, reducing redundant retrieval and unproductive exploration. Second, a domain-knowledge-guided explicit chain-of-thought pruning mechanism converts domain knowledge into fine-grained constraints that guide LLM reasoning-chain generation and prune erroneous paths. This mechanism accelerates convergence and improves optimization stability. Comprehensive experiments are performed on multiple operational-amplifier topologies and five industrial process nodes. The results show that the proposed method substantially reduces the number of circuit simulations while delivering superior optimization performance relative to existing LLM-based approaches. These results indicate that the method improves search efficiency without sacrificing solution quality in practical transistor-level optimization workflows. Its effectiveness across diverse amplifier structures and technology nodes further demonstrates its robustness and industrial applicability. The proposed framework therefore offers an efficient, knowledge-aware solution for LLM-driven transistor sizing optimization under realistic process constraints.