Abstract: The combined use of open-source process design kits (PDKs) and open-source electronic design automation (EDA) tools is important for moving open-source chip development from functional design to manufacturing validation. However, existing open-source tape-out projects have mostly used 130 nm/180 nm processes or virtual processes. End-to-end design closure on a real open-source 55 nm process still lacks systematic validation. To address the limited routing resources, difficult pin access, and high timing sensitivity to load in ICsprout 55, an open-source EDA flow named ECC is developed. ECC achieves end-to-end design closure from RTL to GDSII through timing and routability feedback during placement, sensitivity-guided gate sizing, pin lifting, and design-rule adaptation. All 10 open-source benchmark designs achieved design-rule closure and timing closure under the currently available public rule set. RetroSoC, a SoC design with approximately 70,000 standard cells, was taped out in a multi-project wafer (MPW) run, followed by post-silicon debugging. Based on published papers and public tape-out information, this is the first work to achieve end-to-end design closure and tape-out validation under the “open-source PDK + open-source EDA” model using the open-source ICsprout 55 PDK on a real 55 nm process. The results show that this model can support the full digital chip design flow at a mature nanoscale process node and provide an engineering reference for extending open-source EDA flows to more advanced process nodes.