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    处理器设计自动化:架构到RTL代码的闭环自动设计

    Processor Design Automation: Architecture and RTL Code Generation with Closed-Loop Design Paradigm

    • 摘要: 随着处理器设计复杂度持续提升、设计周期不断压缩以及应用需求快速演进,处理器设计自动化正从面向局部实现的辅助生成,走向覆盖架构设计、寄存器传输级语言生成、验证调试与优化反馈的闭环智能设计范式。现有研究已由早期基于规则、生成器和硬件描述语言的结构化方法,发展到结合机器学习、强化学习、大语言模型与智能体的智能化方法,推动处理器设计在规格理解、方案生成、代码实现、验证修复和性能评估等环节的自动化。系统梳理了处理器设计自动化的发展脉络,从规则与编程语言范式、小模型与强化学习范式、大模型与智能体范式3个阶段总结其代表性思路与能力边界;并围绕从架构到寄存器传输级语言代码的自动生成与设计闭环2条主线,综述生成器、中间表示、可组合变换、多模态规范对齐、电子设计自动化智能体以及分析式、数据驱动和结构化混合评估模型等方向的研究进展。最后,归纳高质量领域数据、多模态规范建模、工具反馈驱动闭环、体系结构早期评估与跨阶段协同优化等关键挑战,为后续处理器设计自动化研究提供参考。

       

      Abstract: As processor design continues to grow in complexity, development cycles are increasingly compressed, and application demands evolve rapidly, processor design automation is shifting from auxiliary generation for localized implementation tasks toward a closed-loop intelligent design paradigm that spans architecture design, RTL generation, verification and debugging, and optimization feedback. Existing research has progressed from early structured approaches based on rules, generators, and hardware description languages to more intelligent methods that incorporate machine learning, reinforcement learning, large language models, and agents, thereby advancing automation across multiple stages of processor design, including specification understanding, solution generation, code implementation, verification and repair, and performance evaluation. This paper systematically reviews the development trajectory of processor design automation, summarizing the representative ideas and capability boundaries of three stages: the rule- and programming-language-based paradigm, the small-model and reinforcement-learning-based paradigm, and the large-model and agent-based paradigm. It further surveys research progress along two main threads: automatic generation from architecture to RTL code, and closed-loop design, covering generators, intermediate representations (IRs), composable transformations, multimodal specification alignment, EDA agents, and analytical, data-driven, and structured hybrid evaluation models. Finally, it identifies key challenges, including high-quality domain-specific data, multimodal specification modeling, tool-feedback-driven closed-loop design, early-stage architectural evaluation, and cross-stage collaborative optimization, with the aim of providing a useful reference for future research on processor design automation.

       

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