Abstract: In modern integrated circuit (IC) design flows, routing quality has a significant impact on key metrics such as chip performance, power consumption, area, and design iteration cost. As a prerequisite for detailed routing, global routing directly affects a design’s detailed routability and the convergence efficiency of design rule violations (DRVs). To address the problem that conventional global routing methods often lack sufficient accuracy in routing resource estimation and allocation, which can lead to numerous DRVs during detailed routing and increase routing iteration cost, this paper proposes a congestion-driven global routing method targeting detailed routability. The proposed method adopts a resource estimation strategy based on a three-dimensional via tree; by jointly analyzing pin distribution and congestion conditions, it builds a fine-grained model of routing resources in pin neighborhoods, thereby improving the accuracy of local routing resource estimation. It further employs a Resource Allocation-based routing guidance strategy, where a net resource map is solved through linear programming to establish an effective routing guidance mechanism and alleviate local congestion caused by unfavorable net ordering. A global routing flow based on sliding-window optimization is also designed; by combining the net resource map with congestion information for two-dimensional routing and layer assignment, the flow further improves routing quality in locally congested regions. Meanwhile, a cross-stage routing information transfer mechanism is established, in which resource estimation results are used for subsequent resource allocation and routing, and the generated net resource map is used to guide global routing, thereby improving routing solution quality and detailed routability. Experimental results show that the proposed method improves detailed routability and reduces the detailed-routing DRV count.