Abstract: Sparse Basic Linear Algebra Subprograms (SpBLAS) are fundamental kernels in artificial intelligence and large-scale scientific computing. Their irregular and dynamic nonzero distributions limit memory bandwidth utilization, compute resource utilization, and system-level communication efficiency. To analyze these bottlenecks, the architectural evolution of domain-specific sparse accelerators is reviewed using an extended Roofline model, and related optimizations are categorized into datapath, compute-core, and array-level coordination. Datapath techniques reduce ineffective data movement through sparse representation, compression, locality-aware reuse, and on-chip memory management. Compute-core techniques improve utilization through sparse-aware execution, redundant-operation reduction, and precision optimization. Array-level techniques alleviate load imbalance and network congestion through spatial interconnects, dynamic scheduling, and communication reduction. Existing studies achieve substantial gains in specific scenarios, but cross-layer coordination remains insufficient because of trade-offs between data supply and computation, bandwidth efficiency and on-chip resource overhead, and operator specialization and system-level generality. Future architectures should explore software-hardware co-compilation, runtime adaptive scheduling, and heterogeneous multi-chiplet integration to improve overall efficiency and generality.