Abstract: Placement for concurrent design planning （CDP） is one of chief techniques in conceptual design of high-performance computers. Because of the difference in target, object, and results, traditional placement methods can not meet the needs of CDP. Based on the traditional placement methods at VLSI and system level, a novel model and algorithm of rapid system level placement for CDP is presented. The basis is hierarchical placement based on the model of directed graph partition. Introducing timing-driven placement to clustering, it is an excellent method which mixes the characteristics of timing-driven placement, clustering, and directed graph partition. The algorithm has been used successfully in the CDP of some super computers.