Abstract: High level synthesis and RTL synthesis are rapidly developed technologies in electronic design automation （EDA）, and retiming is an important method for optimizing design in the back of RTL synthesis. Design and implementation of the software HTC for timing correction based on retiming are introduced in the paper , and some novel algorithms are proposed. These algorithms are approximately optimal methods based on retiming and linear computing complexity, compared with the original retiming algorithm which is optimal and of high computing complexity. The software HTC is tested with a lot of examples and compared with BRT（behavioral retiming） in behavioral compiler of Synopsys, and it is shown that the two tools can achieve the same optimal goal.