Abstract: Due to the increasing system complexity of the hardware design and stringent time-to-market constraint, how to generate high quality test cases to meet the requirement of functional verification is still a major challenge in a typical design cycle. Random test generation technology is one of the most important methods for the verification of modern VLSI. Specifically, coverage directed test generation (CDG), which provides an efficient way for closing a feedback loop from the coverage domain back to the generator that produces potential high quality stimuli to DUV, is the main workhorse in todays random test generation study. Genetic algorithms are intelligent approach to automate the generation of effective solution for black-box optimization without requirements of experience knowledge and resources. In this paper, the authors present GA based CDG, a coverage directed test generation platform, where directives are continuously updated according to feedback based on present functional coverage reports, for the full-chip level verification of microprocessors based on deep discussion and analysis of coverage directed test generation technology using genetic approach. CDG has been taken into practice at the ICT for the verification of a general RISC microprocessor—GODSONI. Experimental results show that CDG can apparently accelerate the verification process and improve the reached coverage from 83.3% to 91.7% compared with original CRPG after about 600 million instructions have been simulated, which implies that verification efficiency is greatly improved and skilled manpower is cut down dramatically.