Abstract: An on-chip decompressor is an efficient method to reduce test cost in multiple scan chain designs. In this paper, a new technique is investigated to implement the decompressor by utilizing combinational circuits. The proposed architecture drives a large number of internal scan chains with far fewer external input pins, thus delivering significant reductions in test data volume. Based on the analysis of compatible relationships among scan slices, the number of external scan inputs can be minimized. The effectiveness and applicability of the proposed scheme are demonstrated by experimental results.