Abstract: To obtain safe and tight WCET estimation, it is necessary to take account of the features of a target processor architecture. New architecture mechanisms, such as cache, pipeline etc., have been widely applied in modern processors to increas their performance. Ignoring their impact will cause WCET overestimated during the analysis of execution time. For the purpose of WCET analysis, a method of modeling MIPS processor architecture is proposed using Petri nets. How to abstract common RISC processor architecture features and how to model them with Petri nets are discussed and its effectivity is verified with experiment.