Abstract: Leakage power has become one of the main restrictions on microprocessor design with the decrease of the transistor's dimension, supply voltage and threshold voltage. Two important techniques to reduce leakage power in caches are sleep cache and drowsy cache in which the cache lines unused recently can be put into low-power mode. A cache leakage power estimation method based on statistics (SB_CLPE) is provided in this paper for sleep cache or drowsy cache and a cache architecture using SB_CLPE is designed which can estimate cache leakage power in real time during the execution of programs. According to the statistics of access intervals for all cache lines, the SB_CLPE can estimate the cache leakage power with different decay interval and get the optimum decay interval which can make the leakage power lowest. For sleep cache, the average variation between the leakage power estimated by SB_CLPE and the leakage power from the HotLeakage power simulator is only 3.16%. The optimum decay intervals estimated by SB_CLPE are almost identical with the real optimum decay intervals from HotLeakage. The cache architecture using SB_CLPE can be used for estimating the optimum decay interval in sleep cache or drowsy cache. By adjusting the decay interval dynamically when programs executes, the best power saving result can be achieved.