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    基于敏感寄存器替换的电路软错误率与开销最优化

    Optimizing Soft Error Rate and Overhead of Circuits Based on Sensitive Registers Replacement

    • 摘要: 随着集成电路的发展,逻辑电路对放射性粒子引起的软错误越来越敏感.现有的电路加固技术通常会带来较大的面积开销.综合考虑电路的软错误率和面积开销,提出一种新的电路加固评估指标FAP,并提出基于贪婪算法的寄存器替换技术,通过将电路的部分敏感寄存器替换为冗余寄存器来免疫电路中的软错误.针对贪婪算法有时不能达到可靠性和开销整体最优的局限,进一步提出可靠性-开销最优的启发式替换算法.实验结果表明,基于贪婪算法的寄存器替换技术只需50%的面积开销就可降低90%的电路软错误率;而可靠性-开销最优的启发式替换算法只需45%左右的面积开销,电路软错误率就降低达90%以上.与其他已有技术相比,电路软错误免疫技术在可靠性和面积开销间达到了更好的折中.

       

      Abstract: Continuous scaling of VLSI technology results in increasing vulnerability to radiation-induced soft errors of combinational and sequential logic circuits. Consequently, soft error issues are playing an important role in design considerations in nanometer integrate circuits. The conventional triple modular redundancy can solve soft error problem, but the serious area overhead are unacceptable. Other existing hardening techniques also lead to large area overhead. We present novel soft error immunity techniques in logic circuits, which can optimize soft error rate and area overhead of logic circuits effectively. Firstly, we propose an evaluation metrics FAP for circuit hardening, considering both circuits’ soft error rate and area overhead. Secondly, we propose an efficient greedy algorithm-based register replacement technique to immunize soft errors, which only replaces most sensitive registers by triple modular redundancy registers in the path of the largest soft error rate. Thirdly, to solve the limitation that greedy algorithm can not achieve optimization between reliability and area, we present a heuristic algorithm which has the best balance in soft error rate and area overhead. Experimental results show that the greedy algorithm can reduce 90% soft error rate with 50% area overhead, while the heuristic algorithm can reduce over 90% soft error rate with only 45% overhead. Compared with previous works, the proposed techniques achieve better tradeoff between soft error rate and area overhead.

       

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