Abstract: Continuous scaling of VLSI technology results in increasing vulnerability to radiation-induced soft errors of combinational and sequential logic circuits. Consequently, soft error issues are playing an important role in design considerations in nanometer integrate circuits. The conventional triple modular redundancy can solve soft error problem, but the serious area overhead are unacceptable. Other existing hardening techniques also lead to large area overhead. We present novel soft error immunity techniques in logic circuits, which can optimize soft error rate and area overhead of logic circuits effectively. Firstly, we propose an evaluation metrics FAP for circuit hardening, considering both circuits’ soft error rate and area overhead. Secondly, we propose an efficient greedy algorithm-based register replacement technique to immunize soft errors, which only replaces most sensitive registers by triple modular redundancy registers in the path of the largest soft error rate. Thirdly, to solve the limitation that greedy algorithm can not achieve optimization between reliability and area, we present a heuristic algorithm which has the best balance in soft error rate and area overhead. Experimental results show that the greedy algorithm can reduce 90% soft error rate with 50% area overhead, while the heuristic algorithm can reduce over 90% soft error rate with only 45% overhead. Compared with previous works, the proposed techniques achieve better tradeoff between soft error rate and area overhead.