Abstract: It is obvious that scan testing is the prevalent design for testability (DFT) in very large scale integrated circuits test. However, scan architecture in digital circuits causes much power consumption because when scan vectors are loaded into a scan chain, the effect of scan-ripple propagates to the combinational logic and redundant switching occurs in the combinational gates during the entire vectors shifting period. Hence, low-power design becomes a challenge for scan test. In this paper, a low-power scan architecture—PowerCut is proposed for minimizing power consumption during scan test, which is based on scan chain modification techniques. Blocking logic using transmission gates is inserted into the scan chain to reduce the dynamic power in shift cycle. At the same time, based on minimum leakage vector, a controlling unit is inserted. It makes the circuit slip into low leakage state during shift cycle. Thus, leakage power is also decreased. Experiments results indicate that this architecture can effectually reduce the power during scan test, and it has little improvement in area or delay overhead, compared with other low cost existing methods.