Abstract: In recent years, many embedded systems must meet the increasing demand of performing computation intensive tasks, such as video decoding, signal processing and so on. General purpose processors (GPPs), although inexpensive, may fail to meet the performance and power cost demands of embedded applications. Thus, it is increasingly common to use application specific instruction set processors (ASIPs) in embedded system designs. These ASIPs can customize hardware computation accelerators for an application domain. Along with instruction set extensions (ISEs), the customized accelerators can significantly improve the performance of embedded processors, which has already been exemplified in previous research work and industrial products. However, these accelerators in ASIPs can only accelerate the applications that are compiled with ISEs. Those applications compiled without ISEs can not benefit from the hardware accelerators at all. Software dynamic binary translation (DBT) is a technique typically used in virtual machines (VMs) to solve the binary compatibility problem and improve the performance. In this paper, we propose using software DBT to overcome this problem, i.e. computation accelerator virtulization. Unlike a static approach, dynamically utilizing accelerator poses many new problems. This paper comprehensively explores the techniques and design choices for dynamic accelerator utilization, and demonstrates the effectiveness by the experimental results.