Abstract: With the rapid development of very large scale integrated circuit (VLSI) manufacturing technologies, more and more transistors can be packed into a single chip. Due to integrating various intellectual-property (IP) cores into a chip, the testing of VLSI is facing enormous challenges. Test data compression techniques based on compression codes are used to reduce ATE memory and test application time and to tackle ATE bandwidth limitation. A new test data compression technique based on symmetry-variable code (SVC) is presented in this paper, which provides significant reduction in test data volume and reduces test cost. Traditional variable-to-variable run length coding techniques based on encoding runs of 0's and runs of 1's. However, there exist numerous don't care bits in the original test set generated by ATPG tool, so the previous methods didn't make use of the characteristics of the test set effectively. As proposed method calculates four types of runs presented symmetrically, it can reduce the length of code words of the runs respectively, and increase the compression ratio. Experimental results for ISCAS89 benchmark and theoretical analysis show that SVC code can provide higher test data compression efficiency than previous codes, and have better adaptability to various test sets. The decoder for SVC is simple and easy to achieve.