RSA快速硬件实现研究
RESEARCH ON FAST HARDWARE IMPLEMENTATION OF RSA
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摘要: RSA加脱密可归结为对 memod N的运算 ,这种大数模幂乘运算可以用字长为 w( 2 w N)的乘法器以迭代的方式来实现 ,对于给定字长的乘法器 ,提高其吞吐速度的有效措施之一是采用流水线技术 .用传统的平行四边形乘法器实现大数模幂乘 ,存在两次迭代之间的数据相关问题 .降低数据相关所引起的时耗代价 ,对于提高时钟频率 ,从而提高乘法器的速度至关重要 .根据矩形乘法器原理设计的 RSA专用部件较好地解决了这一问题 ,HDL 模型的仿真验证了所做设计的正确性 .Abstract: The process of RSA encryption and decryption is to perform the calculation of m e mod N. This modular multiplication can be carried out by using a w-bit multiplier (2 wN) through iteration. Pipelining is one of efficient techniques to increase the throughput for a given word long (w) multiplier. However, by using traditional multiplier, there is data dependency between iterations. To reduce the delay of data dependency, a novel multiplier, named oblong multiplier by its partial product shape is proposed. The new RSA multiplier designed based on the oblong multiplier is up to as twice as fast the traditional one. The gain in speed arises from the faster clock that results from the cut down of data dependency delay cost. The presented multiplier is only a prototype. By taking the advantage of the oblong multiplier arithmetic, a multiplier with pipeline stage at intervals of 1-bit full adder plus latch delay can be designed.
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