Abstract: Dynamic voltage scaling (DVS) technique is an effective way to reduce processor energy consumption through changing the processor’s supply voltage and clock frequency at the runtime. However, the processor energy savings comes at the cost of performance degradation because lowering the operating voltage would increase the circuit delay and slower the processor speed. So, DVS technique needs an algorithm to decide when and how to scale the supply voltage in order to save the processor energy while meeting the performance’s need. A phase-based dynamic voltage scaling algorithm (PBVSA) for the processor’s supply voltage and clock frequency is presented, which uses a state machine based on the instruction working set signature for identifying the change in program and making a decision to adjust the processor’s supply voltage and clock frequency, and sets processor’s supply voltage and clock frequency by estimating and exploiting the frequency scaling β (the ratio of the total off-chip access time to the total on-chip computation time) in each phase. The PBVSA has been realized in the sim-panalyzer. By simulating numerous MiBench benchmarks, the results show that the PBVSA saves on average 29.0% of the processor energy consumption compared with a conventional processor without DVS technique, and the associated performance loss is close to 5.3%.