嵌入式协处理器中除法和平方根计算的整合设计
THE COMBINATIVE IMPLEMENTATION OF DIVISION AND SQUARE ROOT IN AN EMBEDDED COPROCESSOR
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摘要: 在浮点处理元中串行实现除法和平方根计算虽然速度慢 ,但设计简单规则 ,占用资源少 ,有利于嵌入式的应用 .结合嵌入式协处理器 L SC87的研制 ,给出了串行实现除法和平方根计算的基 4SRT算法 ,介绍了确定 SRT选择常数过程中不确定区域的验证方法 ;给出了除法与平方根计算可共用的基 4SRT查询表设计 ;同时讨论了迭代冗余结果向非冗余二进制的转换 .本协处理器设计最大限度地利用了通用数据路径来完成 SRT算法的实现 ,节约了设计资源 ,并缩短了迭代时间Abstract: Although the serial implementation of division and square root converges slowly in the floating point unit, the design simplicity, layout regularity and low layout area make this method popular in embedded application. Based on the development of the embedded coprocessor LSC87, the radix 4 SRT algorithm of the implementation for the combination of division and square root is discussed in this paper. The validity of the uncertain region according to the SRT selection constant is verified and the on the fly conversion of redundant iteration result is designed. The designed radix4 SRT parameters can be applied to the combined two arithmetic calculations. By keeping the general datapath, the shared SRT lookup table could simplify the coprocessor control and decrease the overall iteration steps.
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