Abstract: This paper presents an open VHDL simulation environment OVSE, which includes the modules of compiler, flattener, linker and simulator HSIM to verify the correctness of hierarchical design of digital circuitry at logic level. The open VHDL compiler and the open front and back modules of the simulator are described. These open modules facilitate the incorporation of new developed VHDL tools. The paper also introduces the mechanism of interactive custom commands of HSIM, which will improve the efficiency of verification. Thus OVSE has good expandability and efficiency.