Abstract: The on-chip communication architecture is a fabric that integrates the various SoC（system-on-chip） components, and provides them with a mechanism for the exchange of data. It has a significant impact on SoC performance. The bus based communication architectures are the most popular communication styles up to now. There are mainly two kinds of bus topologies: shared bus topology and crossbar bus topology. There is a great deal of research in the field of system level communication synthesis, but previous bus based communication synthesis research is confined to shared bus synthesis or crossbar bus synthesis. Few works take both shared bus and crossbar bus into account. In this paper, a novel system-level communication synthesis methodology containing crossbar bus and shared bus is presented. Starting with the communication traffic between the system-level processing elements and storage units, the proposed methodology synthesizes an optimal bus topology containing crossbar bus and shared bus. It uses a genetic algorithm to synthesize bus parameters which satisfy the communication delay constraints while considering bus contention and communication synchronization. It models the generated crossbar bus and shared bus at transaction level and optimizes the communication architectures. Experiments show that the proposed methodology results in about 10% component savings when compared with the methodology ever before.