Abstract: A novel architecture for scan-based mixed mode BIST is presented in this paper. To reduce the storage requirements for the deterministic patterns, it relies on a bi-seed compression. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR, and the seeds are again compressed into seeds of a folding counter sequence. The proposed BIST architecture is fully compatible with standard scan design, simple and flexible, so that sharing between several logic cores is possible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility.