Abstract: Supporting multi-standard is becoming the trend of video codec, which brings the challenge of both performance and flexibility in system design. The authors introduce the VLSI implementation of a video codec architecture which can support multiple video coding standards, including H.264/AVC, AVS, and VC-1. Algorithm characteristics of these standards are first analyzed. Based on the algorithm similarities and differences of them, several techniques are efficiently adopted to optimize the architecture at system level and module level. At system level, a four-stage macroblock-based pipeline consists of five programmable cores, and all modules of the encoder and decoder are carefully mapped onto the pipeline architecture. The pipelined multi-core architecture can largely improve system performance by exploiting system level parallelism while maintaining the programmability. And at module level, dedicated data paths are efficiently embedded in the programmable cores to speed up the signal processing. Detailed module level HW/SW partition is proposed according to certain computation in each module. The implementation results show that the codec can guarantee real-time encoding or decoding NTSC （30fps）/PAL （25fps） videos in the worst case, using only 961kgate.