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    AES算法的并发错误检测方法及其VLSI实现

    A Two-Dimensional Parity-Based Concurrent Error Detection Method for AES Against Differential Fault Attack and Its VLSI Implementation

    • 摘要: 提出了一种AES算法的抗差分差错分析的并发错误检测方法——二维奇偶校验方法.与原有的一维奇偶校验方法相比,该方法提供了更为优化的奇偶校验位设置,更重要的是能够同时检测水平和垂直方向上的奇数个错误,在保持了对单个错误的100%的覆盖率的同时,将对多个错误的覆盖率大大提升.由于水平和垂直校验位计算模块可以复用,因此与原有的一维奇偶校验方法相比,该方法增加的硬件开销很小,对硬件实现的关键路径和吞吐率都没有影响,是一种理想的低成本高效率的抗差分差错分析的并发错误检测方法.

       

      Abstract: A two-dimensional parity-based concurrent error detection method for AES algorithm against differential fault attack is proposed. It combines two traditional one dimension parity check methods together to check errors in two directions. A simulation has been conducted to compare the fault coverage of the method in this paper with that of traditional parity-based CED methods. Compared with previous parity-based CED methods, this scheme has a more optimized configuration in choosing the number and position of the parity-check bits. This approach is able to detect odd-bits errors in both horizontal and vertical direction. Therefore it has much higher coverage over multi-bits errors while keeping 100% coverage over odd-bits errors. Since all of the parity calculation modules can be used for both horizontal and vertical parity computation, a pipelined structure is adopted and all parity calculation modules are reusable in both horizontal and vertical parity calculations. The hardware cost of this two-dimensional parity-based CED method is 18%(maximal) higher than that of the traditional methods, whereas the critical path and throughput of this approach remain the same as that of traditional ways. This is a novel CED method for AES algorithm against differential fault attack because of its high efficiency and low cost.

       

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