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    二维测试数据压缩的优化

    Optimization of Two Dimensional Test Data Compression

    • 摘要: 为了减少内建自测试方案中的测试数据,基于输入精简技术(横向压缩)和TRC测试集嵌入技术(竖向压缩)的二维测试数据压缩的BIST方案,采用改进的输入精简算法和基于相容性判断的TRC种子选择算法,同时对横向和纵向压缩进行优化,包括在相同的相容百分数(PC)的条件下,确定位百分数(PSB)对竖向压缩的影响和在相同的PSB条件下竖向压缩算法中的PC对竖向压缩的影响两个方面.针对ISCAS89实验电路的实验结果表明,每一个PSB值都有一个最优的PC值范围[PC\-low_limit,PC\-high_limit]使存储位数最小,并且PSB与最优的PC\-low_limit和PC\-high_limit之间满足近似的线性关系.相对于现有的测试数据压缩方案,采用该优化的二维测试数据压缩方案实现的测试电路,不仅存储位数可减少20%~75%,而且可以达到ATPG工具所能达到的故障覆盖率.另外,测试控制逻辑电路简单,可重用性好.最后,由于在测试向量生成器和被测电路之间没有引入逻辑门,因此,不会对电路的性能产生影响.

       

      Abstract: In order to reduce the storage volume of test data during the built-in self-test (BIST), based on the two dimensional test data compression BIST scheme which combines input reduction (horizontal compression) and TRC test set embedding (vertical compression), the improved input reduction algorithm and TRC seed selection algorithm based on compatibility judging are utilized simultaneously to optimize the horizontal and vertical compression. The optimization includes the influence of percentage of specified bits (PSB) on the vertical compression under the same percentage of compatibility (PC), and the influence of PC on the vertical compression under the same PSB. Experimental results for ISCAS89 benchmark circuits show that there is always a range of PC [PC\-low_limit,PC\-high_limit] which makes the test storage minimal for each PSB, and the relationships between PSB and PC\-low_limit and PC\-high_limit are linear. The proposed two dimensional compression scheme requires 20%~75% less test storage compared with the previous test data compression schemes, and it is indeed possible to embed the entire precomputed test set in TRC sequence. Furthermore, the test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Finally, the proposed approach requires no mapping logic gates between the test generator circuit and the CUT; hence it imposes no additional performance penalty.

       

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