SPARC体系结构
The SPARC Architecture
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摘要: RISC(Reduced Instruction Set Computer)体系结构是一种先进、高效、新型的计算机体系结构。由SUN微系统公司提出的SPARC(scaleable Processor Architecture)结构是它的一种典型的实现。该体系结构集当代软、硬件技术之大成,在指令一级实现平行流水处理,在同一个处理器时钟周期内,有4条硬指令并发执行,从而虽然一条指令需经历取指、译码、执行和写入4个阶段,但从处理机执行指令的速率而言,每个时钟周期,就可(平均地)接近执行完一条指令。这种在不久以前,仅在超大型机上才能实现的技术,已成功地在32位SPARC微机上实现。EST工作站采用了这种结构和技术。SPARC是一种寄存器密集型结构,有大量的组织成窗口的寄存器堆,每个窗口可以用32个r寄存器(包括8个全局寄存器)。窗口数目与实现有关,一般为8个。还有一系列的浮点f寄存器、协处理寄存器、状态寄存器、控制寄存器等。硬件上的进步必然引起程序设计方法与风格的改变。本文从面向汇编语言程序设计角度,介绍SPARC体系结构。Abstract: This paper introduces the SPARC architecture from the viewpoint of assemble language programming The SPARC architecture, proposed byy SUN Microsystem INC., is a typical implementation of RISC technology Its main feutures are as follows: ·simple instruction set·simple and fixed instruction formnt·large "windowed" register file.·delayed coutrol transfer.·pipelining and concurreut execution, nearly one instruction per processor cycle,·supporting floating point and coprocessor interface. The EST Intelli(?) workstation has adopted the SPARC architecture.
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