Abstract: In this paper, a library of VHDL event driven simulation kernel is presented, which is designed to be used in constructing compiled VHDL simulators. The library adopts event driven simulation algorithm to schedule the component, which makes the library apply to both synchronous and asynchronous circuits. Using a multi delay model, it can do function and timing verification at one time. Using multiple data types representation, the library works on multi level design from system behavior level to register translate level and logic gate level. The library implements the event driven simulation algorithm, and accomplishes the task of managing and scheduling discrete events. It provides some interfaces for user designs, and these interfaces make possible and easy the communication between the library and the user designs. By using this simulation kernel library, a specific simulator of user design can be easily and quickly constructed, which leads to a fast verification of VLSI VHDL design. The library was designed using the standard C++ language, and was constructed with C++ classes. It takes use of the polymorphism character of OOP （object oriented programming） in designing the interface providing for user designs. The virtual function in C++ can implement this by defining virtual interfaces, and make all things work straightforward. The simulation kernel library has been tested by combining it with several VHDL designs’ C++ modules, which are achieved by our automatic translation tool BV2C, and the library has proved to have qualities of simplicity, validity, efficiency, extensibility and portability.