Abstract: The imptementation of a simple tester for detecting VLSI DRAM is introduced in this paper. The tester is based on an easy bi-processor system The capacity of a DRAM chip under test is not limited by the addressing ability of the master processor in the system Further, the testing rate of the system is higher than the clock frequency given by the master processor Therefore, the speed limitation of a DRAM can be tested by a lower-speed master processor Five stuck and parts of pattern sensitive defaults can be detected by this system. It can aiso measure the refresh parameter of a DRAM