Abstract: This paper describes the architecture and organization of a multiprocessor system,the Heidelberg POLYP.The architectural features discussed provides very high computing power and high flexibility.The POLYP system is designed modularly and consists of pools of identical processors,a global memory and a host computer.Different types of processors may be used,e.g.16/32 bit general-purpose microprocessors,special-purpose processors (e.g.for low-level image processing tasks),and I/O-processors etc.The total computing power is achieved by independent and parallel operations of a large number of processors.Expected are>100 MIPS for GPPs with a 68000 CPU and correspondingly more for SPPs,e.g. on the pixel level.All modules are interconnected homogeneously by a multiple bus system,the POLYBUS.By choosing an appropriate number of buses n,the I/O and inter-module transfer bandwidth can be adjusted to n×10 Mbytes/sec.For real-time multitasking applications with a prioritized and dynamic task distribution,a second bus system,the SYNCBUS can handle the task/processor scheduling by hardware.Graceful degradation of the system in case of hardware faults is provided.