Abstract: A new architecture for high speed and low power Viterbi decoder is presented in this paper, which is based on a modified T algorithm and modified trace back methods A full parallel and pipeline structure is used to meet the speed requirements, the unnecessary operations in path metric computations are avoided in add compare select unit, and the already generated trace back routes are reused to reduce the number of trace back operations, which contribute to the low power by a clock gating technique By using 0.25μm CMOS process, the （2,1,7） Viterbi decoder is successfully designed and implemented. Its hardware scale is about 50,000 gates （2 input NAND is counted as a gate）, the speed is up to 100MHz, the decoding delay is only 32 clock cycle, and the area is 2 18mm 2 without pads The proposed Viterbi decoder has great chance to be applied to digital communication systems that need high throughput and low power consumption such as DTV and HDTV