Abstract: During the microprocessor design, in order to do the software/hardware co-simulation, the hardware simulator of the microprocessor must be designed before the back-end design of the chip. The hardware simulator of a 32-bit RISC pipeline microprocessor, which is implemented with FPGA, is provided in this paper. Its primary features include: on-chip memory manage unit （MMU）, which is used to realize virtual memory management; on-chip primary cache, which includes instruction cache and data cache; standard SYSAD system interface; on-chip multiply/divide unit （MDU）; precise exception handling. The hardware simulator is implemented with the FPGA xc2v2000 of the XILINX company and its work clock frequency is 30MHz.