基于VHDL高级综合的条码阅读预处理器的FPGA设计

FPGA DESIGN FOR A BAR CODE PREPROCESSOR BASED ON VHDL HIGH LEVEL SYNTHESIS

摘要: 文中定义了条码阅读预处理器的功能，给出其ＶＨＤＬ语言的行为源描述．讨论了在ＶＨＤＬ高级综合系统ＨＬＳ／ＢＩＴ的支持下面向ＦＰＧＡ，从算法级行为描述开始，自顶向下地进行条码阅读预处理器的设计过程．从中可见，ＶＨＤＬ高级综合和ＦＰＧＡ的结合，是一种简化设计复杂度、提高设计时效的设计ＡＳＩＣ的简便方法．

Abstract: The function definition of a bar code preprocessor and its behavior description with VHDL are presented.Starting from the description of the algorithmic level behavior,the FPGA oriented top down design procedure of a bar code preprocessor is studied,which is based on the VHDL high level synthesis system HLS/BIT.It is shown that the combination of VHDL high level synthesis and FPGA can simplify the complexity and increase the efficiency in ASIC design.