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    面向多媒体的并行加速系统中可重构网络结构设计

    RECONFIGURABLE NETWORK STRUCTURE DESIGN IN A MULTIMEDIA-ORIENTED PARALLEL SYSTEM

    • 摘要: 本文讨论了面向多媒体数据处理的并行加速系统硬件平台的设计,采用数字信号处理芯片作为基本的工作单元,提出了一种基于mesh阵列的可重构网络结构设计及其控制方式,并对其性能进行了定性分析。

       

      Abstract: This paper is concerned with the design of the hardware platform for a multimedia-oriented parallel system. A kind of reconfigurable network connection about MIMD on the basis of mesh array is suggested,where the digital signal processing chip TMS320 C30 is adopted as the fundamental unit. Finally, the qualitative analysis of the performance of the reconfigurable mesh is also given.

       

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