Abstract: High peak power makes power distribution network suffer from great instantaneous current and severe electro-migration, resulting in lower chip’s reliability and performance. Thus, it’s very important to effectively estimate an accurate peak power dissipation of a circuit. In order to obtain an efficient estimation of least bound of the peak dissipation of a VLSI chip, a novel approach is proposed in this paper. Experiments with the ISCAS85 benchmarks demonstrate that this approach is time-saving and can give more accurate estimation of peak power not only for the delay-free model, but also for the delay model of maximum power of CMOS circuits.