Abstract: Delayed hardware/software co-verification has become a limitation of embedded system development. Virtual processor is the simulation model constructed before the real processor is made, and software can be debugged on it. The design and implementation of an embedded software design environment based on virtual processor is introduced in this paper. The designer can use the environment to verify the embedded system, both hardware and software, in early design stage. Errors can be encountered and fixed before fabrication, and therefore the design cycle is cut. The environment has been used in an embedded system development process successfully.