容错总线重构机制的研究与实现

STUDY AND IMPLEMENTATION OF THE MECHANISMS OF FAULT TOLERANT INTERCONNECTION BUSES IN A MULTIPROCESSOR SYSTEM

摘要: 在许多高可靠性的应用环境中，对计算机系统的可靠性、可用性要求较高．文中就一种应用到嵌入式系统中的多处理机互连总线的容错、重构机制进行了研究．主要内容包括总线的互连方法、故障检测、总线切换与总线重构．最后给出了实际验证的测试电路和测试结果．

Abstract: The mechanisms of the interconnection buses in a multiprocessor system are presented with emphasis on buses fault tolerance features, fault detection, and bus switch and reconfiguration. The experiment testing circuit and test results are also given.