Abstract: A concurrent error detection（CED） design is proposed for fast discrete cosine transform（FCT）. To achieve the goal of 100 percent fault coverage, FCT is realized by using a butterfly architecture of the B.G.Lee fast algorithm based on DCT\|III. Algorithm\|based fault tolerance（ABFT） is used for error detection because ABFT is a low\|cost system\|level concurrent error detection and fault location scheme. The error detection capability of this scheme is analyzed. When the FCT is implemented with hardware, errors due to finite word length is unavoidable. So the influence of large truncation errors on the throughput and fault coverage is discussed and a conclusion is obtained.