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    ChipletNP: 基于芯粒的敏捷可定制网络处理器架构

    ChipletNP: Chiplet-Based Agile Customizable Network Processor Architecture

    • 摘要: 5G,8K视频等新业务类型不断涌现,使得网络处理器(network processor,NP)的应用场景日趋复杂多样. 为满足多样化网络应用在性能、灵活性以及服务质量保证等方面的差异化需求,传统NP试图在片上系统(system on chip,SoC)上集成大量处理器核、高速缓存、加速器等异质处理资源,提供面向多样化应用场景的敏捷可定制能力. 然而,随着摩尔定律和登纳德缩放定律失效问题的逐渐凸显,单片NP芯片研制在研发周期、成本、创新迭代等方面面临巨大挑战,越来越难以为继. 针对上述问题,提出新型敏捷可定制NP架构ChipletNP,基于芯粒化(Chiplet)技术解耦异质资源,在充分利用成熟芯片产品及工艺的基础上,通过多个芯粒组合,满足不同应用场景下NP的快速定制和演化发展需求. 基于ChipletNP设计实现了一款集成商用CPU,FPGA(field programmable gate array)和自研敏捷交换芯粒的银河衡芯敏捷NP芯片(YHHX-NP). 基于该芯片的应用部署与实验结果表明,ChipletNP可支持NP的快速敏捷定制,能够有效承载SRv6(segment routing over IPv6)等新型网络协议与网络功能部署. 其中,核心的敏捷交换芯粒相较于同级商用芯片能效比提升2倍以上,延迟控制在2.82 µs以内,可以有效支持面向NP的Chiplet统一通信与集成.

       

      Abstract: In order to meet different requirements of performance, flexibility and quality of service in new network scenarios such as 5G and 8K video, network processor becomes increasingly complex and diverse. Traditional network processors try to integrate amount of heterogeneous processing resources such as processor cores, caches and accelerators on a single SoC (system on chip) to provide highly customizable capabilities. However, with the failure of Moore's Law and Dennard's Scaling law, developing one-big network processor becomes unsustainable as it faces greater challenges in R & D cycle, cost and innovation iteration. This paper proposes a novel agile customizable architecture for network processor, namely ChipletNP, which decouples heterogeneous resources and using Chiplet technology to quickly customize new NPs by combining existing mature chip products. ChipetNP is highly flexible as it has an agile switching network which can connect diverse heterogeneous resources with high throughput and predictable delay. We have developed a network processor chip, i.e., YHHX-NP, based on ChipletNP architecture, which integrates commercial CPU, FPGA (field programmable gate array) and agile switching chip. Our results show that ChipletNP supports various emerging network functions such as SRv6 (segment routing over IPv6) with ultra-low latency (<2.82µs), and achieves more than 2\times energy efficiency improvement compared to commercial chips.

       

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