Abstract: A mixed-valued parallel processing complement multiplier is presented in this paper. It has higher integration density, and less hardware cost and time cost than mcitipliers used. In the multiplier, the ordinary binary circuits and the symmetrical 3-valued logic algebra of the Post algebra are used. Input and output of the multiplier are an ordinary binary complement number. In the interior of the multiplier, a redundant number is represented and a no-carry propagate algorithm is used, so that a complicated word operation can become a simple bit operation when a multiplication is operated, and an iterative cellular array multiplier can be builted. For these reasons, the design is simplified, the integration density is raised, and the hardware cost and time cost are decreased.