Abstract: NRS FPU is a coprocessor that is designed and licensed by the Aviational Microelectronic Center. The unified design of floating point multiplication and division sharing general data path with other operations in NRS FPU is presented in this paper. This paper concentrates on the register acting as the division’s index as well as the storage of the multiplier and iteration counter, the table combining BOOTH decoding logic with SRT lookup table, the scaler and the shifter shared by both multiplication and division operation. Finally, most complicated conversion-on-the-fly algorithm is simplified for its implementation. In comparison with other popular microprocessors, NRS FPU is the best choice for the embedded application due to its low area and high speed.