Abstract: Accurate branch prediction is required to achieve high performance in deeply pipelined, wide issue processors Mispredictions waste large numbers of cycles and inhibit out of order execution The effective performance of wide issue processors also depends on instruction window size and instruction fetch bandwidth In this paper, a new more accurate microprocessor model with branch prediction rate and misprediction penalty is presented It is derived from this model that the execution bandwidth requirement increases with the square root of the available number of instructions in the instruction window, and the relations between some of these parameters are explored The tradeoffs among instruction fetch bandwidth, mispredictions penalty, instruction window size, and branch prediction accuracy are discussed The impact of these parameters on instructions per clock is described Thus, the threshold fetch bandwidth, which depends on many processor parameters, and the selection of the parameters can be determined