Abstract: We propose a VLIW architectural model for optimal execution of branch-intensive loops as well as a new single-chip architecture URPR-2 for digital signal and image processing based on this model. In this architecture the instructions belonging to different iterations and different paths can be executed simultaneously. Instruction level parallelism can be exploited in a wider scope as multi-branching can be processed in each machine cycle. A mechanism called the pipeline control blackboard （PCBB） is also proposed to support conditional branches. The URPR2 can not only execute loops with basic block at high speed but also can run loops with conditional branches at a cost of reduced time and space occupancy.