Abstract: RS code is widely used in communication systems, computer systems, storage media, network, and digital television to enhance data reliability; RS（255,223） code is the standard outer code in the concatenated code system of the deep space satellite communication adopted by NASA and ESA. A VLSI design of pipeline RS（255,223） decoder in frequency domain is presented and a pipeline IFFT with 255 points in GF（256） is proposed in this paper. This design is modeled in VHDL; the verified gate level netlist is obtained after synthesizing the VHDL model. The complexity of RS（255,223） decoder is about 200,000 gates, the total latency is 780 cycles, and the throughput is 160Mbps under 20MHz. Comparing with similar designs, this design has smaller latency, moderate area, and high throughput rate.