Abstract: Since increasing number of gates as well as increased sub threshold leakage of the individual transistors result in an increased static leakage current, system on a chip （SOC） ICs in deep submicron technologies present major challenge in the implementation of I DDQ testing While methods such as substrate bias and low temperature test are adequate to reduce sub threshold leakage in deep submicron technologies, almost no solution is available to address the issue of increased leakage due to enormous size of the SOC design Firstly, a design for test concept is presented to deal with the issue of high leakage due to the large size of SOC design Secondly, some design rules are provided, which are necessary to make SOC design suitable for I DDQ testing Finally, the design methodology presented facilitates I DDQ testing by controlling power supply of the individual cores through JTAG instruction registers