The key of IC testing lies in the test patterns generator (TPG) design. Traditional testing methods do not make full use of the test data bit stream to construct test patterns during the test generation and application process, which results in high test cost due to the enormous test data. Test-per-scan scheme exposes the drawback of long test application time with the test data volumes increasing. In order to reduce the test cost, a built-in self test (BIST) scheme based on test-per-clock testing is proposed. Based on the analysis of linear shift test structure, a corresponding forward-backward test patterns generation method is proposed, which efficiently embeds the test set into test-per-clock bit stream. In this method, test patterns are determined by the solution of input-stream with fault dropping, where the input-stream is composed by the first bits of these patterns. The solved minimum input-stream after repeatedly reduction is directly stored in the memory to control the linear shifter in the test application, so as to generate the whole required test set. The experimental results demonstrate that the proposed method, under the precondition of meeting the required fault coverage, can obviously shorten test application time and reduce storage area overhead compared with other approaches.