With the enhancing of integrated circuit technology, the scale of FPGA on-chip resources has increased dramatically, and the quantity of FPGA reconfigurable resources are rising. At the same time, corresponding increasing of the configuration file size and the configuration of reconfigurable system take too long time, which seriously hinder the extension of dynamic reconfigurable system in real-time applications. In order to solve this problem, the main solution at present is to compress the configuration file. We use upper computers to compress the configuration file firstly, and then use configuration circuits to decompress on-chip to reduce the size of the configuration file. In this paper, we propose an algorithm named MH-RLE for the compression of dynamic reconfigurable system configuration files. This algorithm is based on the characteristics distribution of “0” and “1” in a FPGA application binary configuration files. Firstly, the RLE fixed-length compression method is used to compress the configuration file. Secondly, we use the Huffman coding to solve zero placeholders of counters in the RLE fixed-length compression method. Finally, to further enhance the compression rate, we design a bitmask-based function to recompress. Simulation results show that the average compression rate of MH-RLE is 49.82% and comparing with 6 kinds of compression methods, MH-RLE is able to reduce to 12.4%.