In the nanoscale era, the integrated circuit reliability issues caused by both aging mechanism and soft error become very critical. However, there are few researches on combining several factors to analyze the impact of aging mechanism on soft error rate (SER). As a typical aging mechanism, bias temperature instability (BTI) includes negative BTI (NBTI) in PMOS transistors and positive BTI (PBTI) in NMOS transistors. Most of current works focus on single factor affected by NBTI. Based on the research of the effect of gate delay under BTI on SER, the impacts of single event transient (SET) pulse width and critical charge are studied. Firstly, under BTI effect, the variation model of SET pulse width in 32nm technology is completed by considering PBTI; then how to consider SET pulse width and critical charge in the SER calculation is explored, and the variation of SET pulse width can be reflected by that of injected charge during SER estimation is proposed. Based on HSPICE simulations and C++ experiments, it shows that among three factors, delay and SET pulse width have little influence. As a conclusion, the critical charge is a key factor, and SER increases under BTI effect, while the effect is greatest after one year and slows down later.