摘要:
在纳米工艺下，老化效应与软差错共同引发的集成电路可靠性问题至关重要,目前，考虑多个因素分析老化效应对软差错率影响的工作相对较少.作为一种典型的老化效应，偏置温度不稳定性(bias temperature instability, BTI)效应包括发生在PMOS中的负偏置温度不稳定性(negative bias temperature instability, NBTI)和发生在NMOS中的正偏置温度不稳定性(positive bias temperature instability, PBTI)，现有工作多聚焦在单个因素在NBTI下的影响.在BTI作用下门延迟对软差错率(soft error rate, SER)的影响研究工作的基础上，进一步研究了单粒子瞬态(single event transient, SET)故障脉冲宽度和关键电荷对SER的影响.首先通过考虑PBTI,完善了在BTI作用下基于32nm工艺SET脉宽的变化模型；然后分别研究了如何在SER的计算中考虑SET脉宽和关键电荷的影响，提出了SET脉宽变化可以反映在模拟注入电荷量的变化上的结论.通过HSPICE仿真验证和C++实验表明：3个因素中延迟和SET脉宽对SER影响较小，受BTI应力影响SER将增大，应力作用初期影响最为明显，之后影响将变缓.
Abstract:
In the nanoscale era, the integrated circuit reliability issues caused by both aging mechanism and soft error become very critical. However, there are few researches on combining several factors to analyze the impact of aging mechanism on soft error rate (SER). As a typical aging mechanism, bias temperature instability (BTI) includes negative BTI (NBTI) in PMOS transistors and positive BTI (PBTI) in NMOS transistors. Most of current works focus on single factor affected by NBTI. Based on the research of the effect of gate delay under BTI on SER, the impacts of single event transient (SET) pulse width and critical charge are studied. Firstly, under BTI effect, the variation model of SET pulse width in 32nm technology is completed by considering PBTI; then how to consider SET pulse width and critical charge in the SER calculation is explored, and the variation of SET pulse width can be reflected by that of injected charge during SER estimation is proposed. Based on HSPICE simulations and C++ experiments, it shows that among three factors, delay and SET pulse width have little influence. As a conclusion, the critical charge is a key factor, and SER increases under BTI effect, while the effect is greatest after one year and slows down later.
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